The quest for higher performance, increased functionality and lower cost of digital switching circuits has led to high integration density of integrated circuits where more circuit elements are formed at smaller sizes and in greater proximity so that more such elements can be included on a chip of a given size for increased functionality while increasing the number of circuit elements formed by a given sequence of processes and interconnected with shorter connections of reduced capacitance for faster signal propagation and reduced susceptibility to noise. It follows that integrated circuits having the highest performance currently available will also be designed at the limit of the ability to lithographically form features of circuit elements and interconnections with acceptable manufacturing yield. Therefore scaling to smaller sizes is limited by the ability to achieve shorter wavelength or higher numerical aperture exposure systems.
The properties of radiation (e.g. visible light, ultraviolet light, x-rays, etc.) that can be used to expose a pattern on a lithographic resist and properties of lithographic resists cause some effects such as diffraction at mask aperture edges, reflection and scattering of radiation in the resist and, since resist exposure is cumulative, tend to reduce fidelity of the exposed pattern to the exposure mask. These effects are collectively known as optical proximity effects which can sometimes be exploited to improve larger shapes but may unavoidably distort small, closely spaced features produced. In general, optical proximity effects can only be partially compensated.
While not admitted to be prior art in regard to the present invention, to avoid optical proximity effects to the extent possible, so-called pitch split processes have been developed which essentially divide the features to be produced between a plurality of lithographic masks to expose a like plurality of applications of lithographic resist to expose a layer of material on the chip known as a hard mask with the overlaid exposures and then use the in-situ hard mask to form the closely spaced features. Pitch split processes thus allow fewer and more separated features to be formed on each lithographic mask and thus provide possibly the best technique for avoiding or at least reducing optical proximity effects. However, pitch split processes are, by their nature, extremely critical in regard to positioning of the sequence of lithographic exposures and inaccuracy of positioning, known as overlay error must be held to very small distances, often within a few nanometers. Further, each exposure of the exposure sequence must be followed by an etching step, generally reactive ion etching (RIE), for transferring the resist pattern into the hard mask with yet another etching process (also generally RIE) to transfer the hard mask pattern into the desired layer or substrate. Accordingly, a pitch split process is often referred to as a double exposure, double etch process although the number of exposure and etch process can exceed two. The term multiprocess patterning is also used and is more accurately descriptive.
Etching processes are complex and critical (e.g. possibly requiring a sequence of etchants at critical concentrations and temperatures in reaction chambers that may be specific to particular etchants and etching conditions) with relatively small process windows and must be performed to provide especially consistent results in pitch split processes. Such additional complexity cannot be accommodated within the lithography track of current semiconductor manufacturing lines which are generally limited to applying, exposing and developing patterns in a resist. Multiprocess patterning thus requires substantial additional complexity and cost to perform in currently available facilities while the adaptation of manufacturing lines is not feasible due to cost and the different number of pitch split exposures that may be required for different device designs.